The present invention is generally directed to Electronic Design Automation (EDA) for creating integrated circuit products such as, for example, system on chip (SOC) products and the like. More specifically, the present invention is directed to providing expeditious timing signoff verification and correction for a physical circuit design.
While signoff systems and methods are known, such heretofore known systems and methods are encumbered by numerous deficiencies not the least of which are required repeated iterations between timing signoff and physical implementation, wildly divergent timing analyses between timing signoff and physical implementation, inordinate turn around time, untenable storage, processing, and memory requirements, and severely truncated, non-comprehensive analyses.
There is therefore a need for a system and method for expeditious timing signoff for detecting and responsively prescribing physical correction for timing violations in an electronic circuit design defined by physical implementation data.